Cisco Systems announced new additions to its Silicon One unified routing and switching silicon architecture family, including what it called the industry’s first 25.6 Tbps routing chip with a 1.6 Tbps interface.
The announcement comes about 15 months after Cisco unveiled its initial Silicon One devices as part of its broader “Internet for the Future” strategy. Part of the company’s aim with this strategy has been to create convergence in semiconductors used in network routers by traditional telecom service providers and the switching systems of the new crop of massive webscale network operators.
The newest devices in the Silicon One family are the G100, the Q211L and the Q211, bringing the growing Silicon One family to now encompass 10 different semiconductor devices.
Eyal Dagan, senior vice president of the Cisco’s Common Hardware Group, said in a blog post announcing the new Silicon One devices that the new Silicon One G100 “provides the highest performance routing silicon that is 1.7 times higher bandwidth and more than 3 times higher packets-per-second than other routing silicon on the market, and the highest switching performance of 25.6 [Tbps]. With this new device, customers no longer need to choose between programmability, bandwidth, and efficiency.”
The device also includes a 1.6 Tbps interface that dramatically ups the ante on the 400 Gigabit Ethernet interfaces in play today and even can process a single traffic flow at the full 1.6 Tbps. Dagan stated.
With the G100, which is now in the sampling phase with Cisco customers, the vendor also was able to combine programmable functions such as parsing, processing, timestamping, counters, meters,histograms, watermarks, and flow analytics to create a fully programmable temporal view of traffic patterns. “Done in nano-second (nSec) granularity, this programmable infrastructure allows customers to replay past events to truly understand the dynamics of their networks to troubleshoot the equipment, optimize the infrastructure, and identify malicious attacks,” Dagan stated.
The blog post further added, “As networking speeds increase, the Cisco Silicon One fully shared packet buffer plays an increasingly important role in the network. Arbitrary traffic patterns flowing through the G100 can access the entire packet buffer, thereby enabling exceptional network performance under any congestion scenario.”
As for the other new Silicon One devices, Cisco said the Q211L expands on its existing 12.8 Tbps Q200L, 6.4 Tbps Q201L, and 3.2 Tbps Q202L leaf and Top of Rack (TOR) switches. At 8 Tbps with built-in 7nm with 160x56G PAM4 SerDes, customers can build optimized 40x200GE 1RU systems.
Dagan stated that support for advanced SmartTOR features Network Address Translation (NAT) and Port Address Translation (PAT) will help companies simplify their network designs, and that Cisco's advanced hierarchical traffic manager, fully shared packet buffering, and hierarchical Equal-Cost Multi-Path (ECMP) engines can help customers optimize their network performance.
The blog post also said the Q211 "enjoys all the same benefits as the Q211L in a foot-print compatible package but adds even larger table scale and deep packet buffers for routing applications."